1. Field of the Invention
The present invention relates to a data transfer circuit, a solid-state imaging device typically such as a CMOS image sensor and a camera system and, in particular, to a solid-state imaging device and camera system that include a column parallel analog-digital converter.
2. Description of the Related Art
A CMOS image sensor having a column parallel analog-digital converter (which will be abbreviated to ADC hereinafter) is proposed in W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February 1999 (Non-Patent Document 1).
FIG. 1 is a block diagram showing a configuration example of a solid-state imaging device (CMOS image sensor) having a column parallel ADC.
The solid-state imaging device 1 includes a pixel array section 2 functioning as an imaging section, a horizontal scanning circuit 3, a vertical scanning circuit 4, a timing control circuit 5, an ADC group 6, a digital-analog converter (which will be abbreviated to DAC, hereinafter) 7, a counter 8 and a subtracting circuit 9.
The pixel array section 2 has unit pixels 21 laid out in a matrix form. Each of the unit pixels 21 contains a photodiode and an in-pixel amplifier.
In the solid-state imaging device 1, the timing control circuit 5 that generates internal clocks, the horizontal scanning circuit 3 that controls row addresses and/or horizontal scanning and the vertical scanning circuit 4 that controls column addresses and/or vertical scanning are deployed as control circuits for sequentially reading out signals of the pixel array section 2.
The ADC group 6 has an array of multiple ADCs each having a comparator 61 and a memory 62. The comparator 61 compares a ramp waveform RAMP resulting from changing a reference voltage generated by the DAC 7 to have a step shape and analog signals obtained from the unit pixels 21 on the horizontal lines H0, H1 and so on through the vertical lines V0, V1 and so on. The memory device 62 holds the result of counting by the counter 8 that counts the comparison time.
The ADC group 6 has an n-bit-digital signal conversion function and is provided for each of the vertical lines V0, V1 and so on in a column parallel ADC block 63.
The output of the memory devices 62 connects to a horizontal transfer line 64 in a 2-bit width.
Then, 2n sense circuits corresponding to the horizontal transfer lines 64, the subtracting circuit 9 and an output circuit are provided therein.
Now, operations by the solid-state imaging device (CMOS image sensor) 1 will be described in relation with the timing chart in FIG. 2 and the block diagram in FIG. 1.
After the first readout from the unit pixels 21 on an arbitrary row Hx to the vertical lines V0, V1 and so on becomes stable, a step-shaped ramp waveform RAMP in which a reference voltage is changed over time is input to the comparator 61 by the DAC 7, and the comparison with the voltage of an arbitrary vertical line Vx is performed in the comparator 61.
In parallel with the input of the step-shaped waves of the ramp waveform RAMP, the counter 8 performs the first counting.
Here, the output of the comparator 61 is inverted when the voltages of the RAMP and the Vx are equal, and, at the same time, the count based on the comparison period is held in the memory device 62. The first readout reads out a reset component ΔV of the unit pixel 21, and the reset component ΔV internally contains noise that varies among the unit pixels 21 as an offset.
However, the variation of the reset component ΔV is generally small, and the reset level is common in all pixels. Therefore the output of an arbitrary vertical line Vx is almost known.
For that reason, the comparison period can be reduced by adjusting the ramp waveform (RAMP) voltage upon the first readout of the reset component ΔV. In this example, the ΔV comparison is performed in a count period for seven bits (which is equal to 128 clocks).
The second readout reads out a signal component corresponding to the quantity of incident light for each of the unit pixels 21 in addition to the reset component ΔV and performs the same operation as that of the first readout.
That is, after the second readout from the unit pixels 21 on an arbitrary row Hx to the vertical lines V0, V1 and so on becomes stable, a step-shaped ramp waveform RAMP in which the reference voltage is changed over time is input to the comparator 61 by the DAC 7, and the comparison with the voltage of an arbitrary vertical line Vx is performed in the comparator 61.
In parallel with the input of the step-shaped waves of the ramp waveform RAMP, the counter 8 performs the second counting.
Here, the output of the comparator 61 is inverted when the voltages of the RAMP and the Vx are equal, and, at the same time, the count based on the comparison period is held in the memory device 62.
At that time, the first count and the second count are held at different places within the memory device 62.
After the completion of the AD conversion period above, the first and second n-bit digital signals held in the memory device 62 by the vertical scanning circuit 4 undergo the processing of (second signal)-(first signal) sequentially in the sense circuit and subtracting circuit 9 through the 2n horizontal transfer lines 64. After that, the same operation is performed for each row sequentially, and a two-dimensional image is created.